The present invention relates to a semiconductor memory device and, particularly, to a technology that can be particularly effective when adapted to a memory system for multi-level data in a nonvolatile semiconductor memory device, such as a nonvolatile memory device (hereinafter simply referred to as a flash memory) which is capable of electrically erasing a plurality of stored data at one time.
In a flash memory, a nonvolatile memory element having a control gate and a floating gate is used as a memory cell, and the memory cell is constituted by a single transistor. In such a flash memory, the programming operation is carried out by applying a voltage of about 4 V(Volt) to the drain region of the nonvolatile memory element as shown in FIG. 21, applying a voltage of about −10 V to a word line to which a control gate CG is connected, and discharging the electric charge from the floating gate FG by using a tunneling current to establish a state of a low threshold voltage (logic “0”). To carry out the erasing operation, as shown in FIG. 22, a voltage of about −3 V is applied to the well region, to the drain region and to the source region, and a voltage of as high as 10 V is applied to the control gate CG to generate a tunneling current in order to inject a negative charge into the floating gate FG and to maintain a high threshold value (logic “1”). Thus, data of one bit is stored in a memory cell.
There has been proposed the concept of a so-called “multi-level” memory to store data of two or more bits in a single memory cell in order to increase the storage capacity. An example of such a multi-level memory has been disclosed in, for example, Japanese Patent Application H7-14031 (14031/1995) which corresponds to U.S. patent application Ser. No. 08/860,793.
In such a multi-level memory of the above-mentioned patent application, consecutive two-bit data “01”, “00”, “10” and “11” are subjected to logical conversion, and are stored correspondedly to one of the threshold voltage ranges of 1.2V or lower, 1.6 to 2.3 V, 2.8 to 3.5 V, and 4 V or higher of the memory cell as shown in FIG. 23. In the above-mentioned memory, therefore, it is impossible to identify the stored data unless a reading operation is executed three times while successively changing the level of the word line to, e.g., 1.4 V, 2.6 V, 3.7 V, causing a drawback in that a long time is needed to read the data.